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New 3D Flash Memory Chips Cut Autonomous Vehicle Navigation Energy Use By 74%
In A Nutshell
- Seoul National University researchers created chips that process navigation data where it’s stored rather than moving it between memory and processors, cutting energy use by up to 74% in direct tests.
- The laboratory system combines road extraction from satellite images with route optimization, achieving over 90% accuracy in matching predicted roads to actual locations across 1,438 test images.
- Diagonal wiring patterns and natural electrical fluctuations replace traditional hardware components, with the design achieving 89% smaller area and 91% lower energy in the memory arrays compared to conventional approaches.
- The technology works with standard chip manufacturing processes and successfully planned optimal routes across 49 different road networks with 100% success after training.
Self-driving vehicles are certainly convenient. However, logistically, they constantly face the computational challenge of processing satellite imagery to identify roads before calculating efficient paths through those networks.
In pursuit of a solution, researchers at Seoul National University have developed a chip architecture that handles both tasks while consuming significantly less power than traditional systems. They successfully demonstrated the approach in laboratory hardware and simulations, showing how such chips could eventually be integrated into autonomous vehicle systems.
The team, led by Jong-Ho Lee, built what they call “in-memory path planning” systems using vertically stacked 3D flash memory. Published in Science Advances, the research demonstrates how artificial intelligence hardware can simultaneously recognize roads from satellite images and determine optimal routes without the energy-hungry data transfers that plague conventional computing.
Path planning algorithms determine where autonomous vehicles should drive based on road data gathered from satellites or drones. Current approaches require separate processing stages: first extracting road information through convolutional neural networks, then using reinforcement learning to select routes that minimize travel time and fuel consumption. Each stage typically demands its own specialized hardware, creating inefficiencies in both physical footprint and power draw.
Computing Where Memory Lives Eliminates Energy Waste
The Seoul National team reimagined how information moves through computer chips. Rather than shuttling data back and forth between separate memory and processing units, their system performs calculations directly within the memory arrays themselves. This compute-in-memory approach eliminates the data transfer bottleneck that constrains conventional processors.
At the heart of their innovation sits an unusual geometric arrangement. Where conventional memory arrays organize connections in perpendicular grids, the researchers angled their wiring diagonally. This allows the chip to perform image convolutions without the redundant “off-state” cells that waste space and leak current in standard designs.
Image convolution, a mathematical operation that extracts features like edges and textures from photos, normally requires a filter to slide across an image both horizontally and vertically. Traditional chip architectures handle this by either creating massive arrays with mostly unused cells, or by processing each position sequentially.
The diagonal layout processes horizontal movements in parallel while requiring time steps only for vertical slides. When extracting roads from a 128-by-128 pixel satellite image, the system completed the task using fewer devices than conventional approaches while maintaining accuracy.
Overall concept of IMPP for autonomous driving. (Credit: Jong-Ho Lee, et al, Science Advances)
Road Recognition From Satellite Images Reaches Near-Perfect Accuracy In Self-Driving Cars
On the Massachusetts Roads Dataset of 1,438 satellite images, the system was assessed with IoU and Dice metrics and kept high performance with no noticeable drop at the measured device variation. The system extracts road features from satellite data, down-samples the results to a manageable grid size, then determines optimal paths through the identified road network.
The physical structure builds on 3D flash memory technology already used in consumer storage devices. Six memory cells stack vertically in each unit, allowing much higher density in the same physical footprint compared to flat designs. Each floor sits electrically isolated from its neighbors, preventing interference between layers.
Once roads are extracted from satellite images, the system determines which route reaches the destination in the fewest moves. This requires reinforcement learning, where an artificial agent explores different paths and gradually learns which choices lead to better outcomes.
Electrical Noise Teaches Chips To Explore Routes
Exploration presents a problem for hardware systems. Software-based reinforcement learning typically uses random number generators to inject variability into early decisions. Hardware implementations usually require additional circuitry to generate this randomness, adding cost, complexity, and power consumption.
The researchers discovered their flash memory cells already contained a suitable randomness source. Electrical current flowing through the silicon channels fluctuates according to a pattern called 1/f noise, arising from charge movement through the crystalline structure. These fluctuations follow a predictable statistical distribution with an amplitude that decreases as operating voltage increases.
By treating this inherent noise as a deliberate design feature, the team eliminated the need for separate exploration circuitry. In early learning stages, when the system hasn’t yet identified good paths, the noise causes it to try varied routes. As training progresses and certain routes prove superior, the difference in signal strength between good and bad choices grows large enough that noise no longer changes decisions.
The system receives road features from satellite data, then determines the best paths forward. (Credit: Scharfsinn on Shutterstock)
Testing on navigation tasks within a 6-by-6 grid, the system initially wandered randomly near starting points. After discovering routes to endpoints, it consistently selected optimal paths. Removing the noise from simulation prevented the system from learning at all.
The researchers tested their complete path-planning system on 49 different road networks extracted from the Massachusetts dataset. Success rates reached 100% after sufficient training, with the system consistently identifying optimal routes regardless of road complexity.
In tests on a standard image-recognition benchmark called CIFAR-10, the 3D-memory chips ran a VGG-11 neural network with results nearly identical to the software version. Even when the researchers factored in small differences in how individual memory cells conducted electricity, the chip’s accuracy stayed the same.
Manufacturing Compatibility Speeds Commercial Potential
The blocks handling image convolution and those performing reinforcement learning differ only in their top-layer metal wiring patterns. Both use identical underlying 3D flash memory structures. This means fabricators can produce both block types on the same silicon wafer without additional process steps.
When benchmarked against other cutting-edge memory technologies including resistive RAM, ferroelectric transistors, and various memristor designs, the 3D flash architecture showed better efficiency particularly for tasks involving larger images. The energy savings came from multiple sources: eliminated data transfers, reduced redundant cells, and parallel processing.
The team fabricated their devices on 6-inch silicon wafers using processes compatible with existing semiconductor manufacturing infrastructure. The ability to use established fabrication techniques could accelerate the path from laboratory demonstration to commercial deployment.
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The research acknowledges several constraints. Temperature variations can influence the conductance of 3D flash memory cells by accelerating charge detrapping in the charge-trap stack, potentially altering synaptic weights and reducing accuracy of calculations. The study notes these effects can be mitigated through circuit-level compensation methods such as adaptive read-bias adjustment or periodic calibration. The structural advantages of the 3D array help limit temperature-sensitive voltage drop variation. Additionally, optimizing the gate dielectric stack or improving the quality and thickness of the tunneling oxide can further suppress thermally induced instability at the device level.
The study tested the system primarily on the Massachusetts Roads Dataset and CIFAR-10 benchmark. Performance on other datasets or in real-world autonomous driving scenarios with more complex road networks remains to be demonstrated. The 1/f noise level varies with drain current and device size, requiring optimization for specific tasks. The research notes that in sparse-reward environments, excessive reliance on stochastic exploration may hinder efficient policy learning by causing the agent to drift without meaningful reward feedback.
This work was supported by the BK21 FOUR program of the Education and Research Program for Future ICT Pioneers at Seoul National University, the National R&D Program through the National Research Foundation of Korea funded by the Ministry of Science and ICT (RS-2023-00258527), and the National Research Foundation of Korea grant funded by the Korea government (MSIT) (RS-2025-00517999). The authors declare no competing interests.
Im, J., Kim, J., Ko, J., Shin, W., Koo, R.H., Kim, J., Lee, J.H. (2025). “Hybrid functional 3D artificial synapses for convolution and reinforcement learning,” published November 14, 2025 in Science Advances, 11, eadw7498. DOI: 10.1126/sciadv.adw7498. Authors are affiliated with the Department of Electrical and Computer Engineering and Inter-university Semiconductor Research Center at Seoul National University, Seoul, Republic of Korea; Department of Electronic Engineering and Department of System Semiconductor Engineering at Sogang University, Seoul, Republic of Korea; and Department of Semiconductor Convergence Engineering at Sungkyunkwan University, Suwon, Republic of Korea.
