Credit: CC0 Public Domain
A research team, led by Professor Heein Yoon in the Department of Electrical Engineering at UNIST has unveiled an ultra-small hybrid low-dropout regulator (LDO) that promises to advance power management in advanced semiconductor devices. This innovative chip not only stabilizes voltage more effectively, but also filters out noise—all while taking up less space—opening new doors for high-performance system-on-chips (SoCs) used in AI, 6G communications, and beyond.
The new LDO combines analog and digital circuit strengths in a hybrid design, ensuring stable power delivery even during sudden changes in current demand—like when launching a game on your smartphone—and effectively blocking unwanted noise from the power supply.
What sets this development apart is its use of a cutting-edge digital-to-analog transfer (D2A-TF) method and a local ground generator (LGG), which work together to deliver exceptional voltage stability and noise suppression. In tests, it kept voltage ripple to just 54 millivolts during rapid 99 mA current swings and managed to restore the voltage to its proper level in just 667 nanoseconds. Plus, it achieved a power supply rejection ratio (PSRR) of –53.7 dB at 10 kHz with a 100 mA load, meaning it can effectively filter out nearly all noise at that frequency.
Another major advantage is its size—at only 0.032 mm² when made with a 28-nanometer CMOS process—thanks to the elimination of bulky external capacitors. This tiny footprint makes it ideal for highly integrated SoCs, where multiple functions need to be packed into a small space.
Lead researcher Changmin An explained, "Traditional hybrid LDOs often require large capacitors to smooth out digital-to-analog transitions, which can be a bottleneck. Our new design solves this problem with a seamless digital-analog transfer technique, making it both smaller and more efficient."
Designed to activate only when needed during sudden power surges, this LDO also consumes very little standby power. Its overall performance, measured by a comprehensive figure of merit (FoM), is a remarkable 0.029 picoseconds—setting a new global benchmark.
Professor Yoon added, "This ultra-compact, low-power LDO offers outstanding voltage stability and noise reduction, making it highly suitable for next-generation AI chips and 6G communication modules. It's a versatile solution that can be widely adopted across high-performance electronics."
The findings are published in the IEEE Journal of Solid-State Circuits.
Provided by UNIST
